The present invention relates to a vertical semiconductor structure that facilitates realizing both a high breakdown voltage and a high current capacity in insulated gate field effect transistors (MOSFET""s), insulated gate bipolar transistors (IGBT""s), bipolar transistors, diodes and such semiconductor devices. The present invention relates also to a method of manufacturing the semiconductor device with such a vertical semiconductor structure.
In vertical semiconductor devices, a current flows between electrodes disposed on both major surfaces opposing each other. For providing the vertical semiconductor devices with a higher breakdown voltage, it is necessary to form a thick highly resistive layer between the electrodes. However, the thick highly resistive layer inevitably causes a higher forward voltage for making a current flow between the electrodes and a higher ON-resistance. The higher forward voltage and the higher ON-resistance further cause loss increase. In short, there exits a tradeoff relation between the forward voltage and the breakdown voltage or between the ON resistance (current capacity) and the breakdown voltage.
EP0 053 854, U.S. Pat. No. 5,216,275, U.S. Pat. No. 5,438,215 and Japanese Unexamined Laid Open Patent Application H09 (1997)-266311 disclose semiconductor devices that include a drift layer including heavily doped n-type regions and p-type regions alternately laminated with each other to solve the foregoing problems. The alternately laminated n-type regions and p-type regions are depleted to bear the breakdown voltage in the OFF-state of the device.
FIG. 18 is a cross section of a part of the vertical MOSFET according to an embodiment of U.S. Pat. No. 5,216,275. The vertical MOSFET of FIG. 18 is different from the conventional vertical semiconductor devices in that the vertical MOSFET of FIG. 18 includes a drift layer 12, that is not single-layered but formed of n-type drift regions 12a and p-type partition regions 12b alternately laminated with each other. In the figure, there is a p-type well region 13, an n+-type source region 14, a gate insulation film 15, a gate electrode 16, a source electrode 17, and a drain electrode 18. Although a drift current flows through n-type drift regions 12a, n-type drift regions 12a and p-type partition regions 12b will be collectively referred to hereinafter as drift layer 12.
Drift layer 12 is formed in the following way. First, a highly resistive n-type layer is grown epitaxially on an n+-type drain layer 11. The n-type drift regions 12a are formed by etching the highly resistive n-type layer to form trenches down to n+-type drain layer 11. Then, p-type partition regions 12b are formed by epitaxially growing p-type layers in the trenches.
Hereinafter, the semiconductor device, including an alternating conductivity type drift layer that provides a current path in the ON-state of the device and is depleted in the OFF-state of the device, will be referred to as a xe2x80x9csemiconductor device with an alternating conductivity type layerxe2x80x9d.
The dimensions described in U.S. Pat. No. 5,216,275 are as follows. When the breakdown voltage is put in VB, the thickness of the drift layer 12 is 0.024VB1.2(xcexcm). When n-type drift region 12a and p-type drift region 12b have the same width b and the same impurity concentration, the impurity concentration is 7.2xc3x971016VBxe2x88x920.2/b (cmxe2x88x923). If VB is 300 V and b is 5 xcexcm, the drift layer 12 will be 23 xcexcm in thickness and the impurity concentration 4.6xc3x971015 cmxe2x88x923. Since the impurity concentration for the single-layered drift layer is around 5xc3x971014 cmxe2x88x923, the on-resistance is reduced by drift layer 12. However, when using conventional epitaxial growth techniques, it is difficult to bury a good quality semiconductor layer in such a narrow and deep trench (with a large aspect ratio).
The tradeoff between the on-resistance and the breakdown voltage is also commonly encountered in lateral semiconductive devices. The foregoing EP0 053 854, U.S. Pat. No. 5,438,215 and Japanese Unexamined Laid Open Patent Application H09(1997)-266311 disclose lateral semiconductor devices with an alternating conductivity type layer and methods, common to the lateral semiconductor devices and vertical semiconductor devices, for forming the alternating conductivity type layer which employ the selective etching technique for digging trenches and the epitaxial growth technique for filling the trenches.
However, it is difficult to employ the selective etching technique for digging trenches and the epitaxial growth technique for filling the trenches in manufacturing the vertical semiconductor devices with an alternating conductivity type layer as explained with reference to U.S. Pat. No. 5,216,275. Japanese Unexamined Laid Open Patent Application H09 (1997)-266311 describes the nuclear transformation by a neutron beam and such radioactive beams. However, such nuclear transformation processes require large facilities and can not be used easily.
In view of the foregoing, it is an object of the invention to provide a semiconductor device with an alternating conductivity type layer that reduces the tradeoff relation between the forward voltage or the ON-resistance and the breakdown voltage. It is another object of the invention to provide a semiconductor device with an alternating conductivity type layer and with a high breakdown voltage that facilitates increasing the current capacity by reducing the forward voltage and the ON-resistance. It is still another object of the invention to provide a method for manufacturing such a semiconductor device with an alternating conductivity type layer easily and with excellent mass-productivity.
According to an aspect of the invention, there is provided a method of manufacturing a semiconductor device including: a layer with low electrical resistance having a first surface and a second surface, an electrode on the second surface of the layer with low electrical resistance, a pn-laminate having a first surface contacting the first surface of the layer with low electrical resistance and a second surface opposing the first surface thereof, at least one electrode on the second surface of the pn-laminate; and the pn-laminate formed of drift regions of a first conductivity type and partition regions of a second conductivity type opposite to the first conductivity type extending vertically between the first surface and the second surface of the pn-laminate in parallel to each other and arranged alternately with respect to each other horizontally, the pn-laminate providing a current path when the semiconductor device is ON and being depleted when the semiconductor device is OFF, the method including the steps of: implanting impurity ions; and treating the implanted impurity ions thermally thereby to form the drift regions or the partition regions.
Ion implantation and thermal treatment are well established techniques for forming a region of one conductivity type more easily than the other conventional techniques which need to dig a trench with a large aspect ratio and to fill the trench with an epitaxial layer. Advantageously, the acceleration voltage for implanting the impurity ions is changed stepwise.
By implanting impurity ions through multiple steps by changing the acceleration voltage stepwise, regions continuous in the depth direction thereof are formed.
Advantageously, the acceleration voltage for implanting the impurity ions is changed continuously to form regions which have a uniform width and are continuous in the depth direction thereof.
When the drift regions or the partition regions are formed by ion implantation, the partition regions or the drift regions are formed advantageously by epitaxial growth, by ion implantation or by thermally diffusing impurity ions from the surface.
When the drift regions or the partition regions are formed by diffusing impurity ions from the surface of an epitaxial layer or a diffusion layer, the partition regions or the drift regions are formed advantageously by implanting impurity ions from the surface of the epitaxial layer or the diffusion layer and by treating the implanted impurity ions thermally. Advantageously, the drift regions and the partition regions are formed by implanting respective impurity ions almost simultaneously and by treating the implanted impurity ions thermally.
According to another aspect of the invention, there is provided a method of manufacturing a semiconductor device including a layer with low electrical resistance having a first surface and a second surface, an electrode on the second surface of the layer with low electrical resistance, a pn-laminate having a first surface contacting the first surface of the layer with low electrical resistance and a second surface opposing the first surface thereof, at least one electrode on the second surface of the pn-laminate; and the pn-laminate formed of drift regions of a first conductivity type and partition regions of a second conductivity type opposite to the first conductivity type extending vertically between the first surface and the second surface of the pn-laminate in parallel to each other and arranged alternately with respect to each other horizontally, the pn-laminate providing a current path when the semiconductor device is ON and being depleted when the semiconductor device is OFF, the method including the steps of: forming a layer for forming the drift regions and the partition regions; introducing impurity ions into the surface portions of the layer for forming the drift regions and the partition regions, and diffusing the introduced impurity ions thermally thereby to form the drift regions, the partition regions and pn-junctions between the drift regions and the partition regions.
When the drift regions and the partition regions are arranged closely and alternately to each other by the quite well established ion introduction into the surface portions and by the quite well established thermal diffusion, pn-junctions are formed between the drift regions and the partition regions.
According to a further aspect of the invention, there is provided a semiconductor device including: a layer with low electrical resistance having a first surface and a second surface; an electrode on the second surface of the layer with low electrical resistance; a pn-laminate having a first surface contacting the first surface of the layer with low electrical resistance and a second surface opposing the first surface thereof, at least one electrode on the second surface of the pn-laminate; and the pn-laminate formed of drift regions of a first conductivity type and partition regions of a second conductivity type opposite to the first conductivity type extending vertically between the first surface and the second surface of the pn-laminate in parallel to each other and arranged alternately with respect to each other horizontally, wherein the pn-laminate provides a current path when the semiconductor device is ON and is depleted when the semiconductor device is OFF.
Advantageously, the junction depth y between the drift regions and the partition regions is large than the width x of the drift regions and the partition regions.
When the depth y of the junctions between the drift regions and the partition regions is large than the width x of the drift regions and the partition regions, depletion layer expand first for the full widths of the drift regions and the partition regions and, then, downward.
Advantageously, the junction depth yp of the partition regions is larger than the junction depth yn of the drift regions.
When the junction depth yp of the partition regions is smaller than the junction depth yn of the drift regions, the lower portions of the drift regions extended more deeply than the partition regions will not be depleted, causing the reduced breakdown voltage.
Advantageously, the junction depth yp of the partition regions is related with the junction depth yn of the drift regions by a relational expression yn less than ypxe2x89xa61.2 yn.
The junction depth yp of the partition regions much larger than the junction depth yn of the drift regions is useless.
Advantageously the semiconductor device further includes a lightly doped layer of the first conductivity type below the partition regions. Preferably, the thickness tn of the lightly doped layer of the first conductivity type is smaller that the junction depth yp of the partition regions.
The lightly doped layer of the first conductivity type is a highly resistive layer that increases the forward voltage and the ON-resistance. When the lightly doped layer of the first conductivity type is thick, depletion layers tend to expand and the expanded depletion layers narrow the current path, causing the JFET effect. Therefore, the forward voltage and the ON-resistance are increased.
Advantageously the second surface of the layer with low electrical resistance and the second surface of the pn-laminate (the major surfaces) are parallel to a (110) plane of a silicon crystal. When the major surface is a (110) plane of a silicon crystal, impurity ions may be implanted by utilizing the channeling effect under the same acceleration voltage more than twice